Ho presentato la mia candidatura online. La procedura ha richiesto 2 giorni. Ho sostenuto un colloquio presso Ambarella (Santa Clara, CA)
Colloquio
The Interviewer just asked about the project in your resume:
the company need someone who can use verilog, and understand the layout of your design.
No hiring entry-level engineer
Altre recensioni di colloqui per Analog Design Engineer presso Ambarella
La procedura ha richiesto 2 settimane. Ho sostenuto un colloquio presso Ambarella (Santa Clara, CA) nel mese di nov 2012
Colloquio
I got a phone interview and after less than a week I was told to arrange an on-site interview. Almost all interview questions are technical but basic. Familiarity to the topics and speed of response to those questions may be critical.Though the questions are not easy, the people interview me are quite kind.
Domande di colloquio [1]
Domanda 1
1. What are DNL and INL of an ADC? What's the difference?
2. What's quantization noise? Derive signal-to-quantization-noise ration.
3. How to compensate an OPAMP?
4. When the size of tail current transistor increase, how will it affect the phase noise of a VCO?
