Ho presentato la mia candidatura tramite l'università. La procedura ha richiesto 2 giorni. Ho sostenuto un colloquio presso Synopsys nel mese di apr 2015
Colloquio
There were 3 tests, First was a practical in which we were asked to design, simulate & synthesize for a given specification, using system verilog. It was not difficult.
2nd was an objective test on digitals & aptitude.
3rd test was on analog & aptitude.
Shortlisted candidates had FF technical Interview, further selected candidates had telephonic HR round.
Domande di colloquio [1]
Domanda 1
Frequency dividing circuits, shell & perl scripting, digital concepts, Data Structures.
i had to go through 2 different phases: the technical and the hr. The former lasted about 2 hour with the senior manager of the analog design department, while the latter lasted 1 hour and was mainly discussion about the salary and duration of contract
Domande di colloquio [1]
Domanda 1
Trade off of using NMOS and PMOS devices while designing an LDO
Ho presentato la mia candidatura tramite l'università. Ho sostenuto un colloquio presso Synopsys
Colloquio
Online using zoom two interviewers, each one asking both technical and behavior questions. One hour interview . Interviewer are very nice and kind they are more care about the way you solve the problem instead of the final answer
Ho presentato la mia candidatura online. Ho sostenuto un colloquio presso Synopsys nel mese di dic 2024
Colloquio
Consisted 2 rounds of interviews each 45 mins long.
Verilog (design,test benches, output graphs), some aptitude questions, programming in prefered language and resume based questions were asked.
Oops concepts were asked
Domande di colloquio [1]
Domanda 1
Verilog (design,test benches, output graphs), some aptitude questions, programming in prefered language and resume based questions were asked.
Oops concepts were asked
