Ho sostenuto un colloquio presso Synopsys (Bengaluru)
Colloquio
Simple and basic digital electronics questions were asked. Some Questions on verilog and HDL was also included. Basic system verilog and OOPS concepts are necessary. A good understanding of projects presented in the resume is very essential.
Having knowledge of fundamentals of VLSI will be helpful.
Ho sostenuto un colloquio presso Synopsys (Ottawa, ON)
Colloquio
It was a smooth process, mostly technical problems, no tricky questions. Mostly asked about previous project on resume, with some coding questions at the end. Total 4hr with 4 different engineer/manager
The interview process consisted of two rounds. The first was a technical screen focusing on Verilog and RTL design. The second was a behavioral interview with the manager. nice processes overview
Ho presentato la mia candidatura tramite segnalazione di un dipendente. Ho sostenuto un colloquio presso Synopsys nel mese di mar 2025
Colloquio
hard. fifo's n all. and other designing questions. muxes, gates, cdc n all. designing n other implementation questions are their . tough questions were their. U get designing to the best.
Domande di colloquio [1]
Domanda 1
ok. fifo..design n implementation.and other designing questions
