The questions are as follows : Difference between validation and verification ? What is Race condition? Difference between Latch and flipflop? How to design ROM? What is a State machine? Cycle driven and event driven simulation differences and which one is better Functional and code coverage differences Blocking and non-blocking assignments in Verilog How to define variables in Verilog? $display and $monitor differences Setup and hold time Hold time violation Mesi protocol Page table DRAM and SRAM differences and how to design them

FIFO explanation and verilog code for it