Rd #1:
> explain the complete RTL design of Async FIFO; with individual blocks - synchronizer, counter/ pointer, comparator, memory modules
> what is meat-stability and how did you resolve it in FIFO; made use of gray code pointers
> given a boolean logic, was asked to implement it using only NAND gates
> write pseudo code for binary search, linear search
Rd #2
> explain directed testing and random testing; explained with FIFO as an example
> practical scenarios wrt SOC design - how feasible it is to turn on/ off a block, voltage/ freq scaling - which one to scale first while up/ down scaling
> was asked to draw the block diag of PLL and explain individual components (from resume)
> how to check if a design is functionally correct; functional coverage, code coverage, random testing for bugs
Rd #3
> write truth table of 2 i/p nand gate, draw transistor level diag including sizing, explain the working wrt a particular case
> write pseudo code in C/C++ or SV for given problem statement
> verilog code of comparator
Rd #4
> resume/ course oriented questions
> interconnect delay, repeater insertion etc
> questions on floor planning and place and route
Rd #5
> signal integrity - cross talk, IR drop, EM, Antenna effect; ways to reduce it
> from resume, asked to draw floor plan of one of my projects (SRAM memory bank)