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      Colloqui di Intel CorporationColloqui per Graphics Hardware Engineer presso Intel CorporationColloquio di Intel Corporation


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      Colloquio per Graphics Hardware Engineer

      29 apr 2015
      Dipendente anonimo
      Folsom, CA
      Offerta accettata
      Esperienza positiva
      Colloquio nella media

      Candidatura

      Ho presentato la mia candidatura tramite segnalazione di un dipendente. La procedura ha richiesto 3 mesi. Ho sostenuto un colloquio presso Intel Corporation (Folsom, CA) nel mese di apr 2015

      Colloquio

      I applied trough my friend. After 3 months, I got a call for phone call interview (1hr). I answered all the questions. Next day, I got confirmation for Onsite Interview. I had 10 days to prepare. After 2 days, I got the confirmation.

      Domande di colloquio [1]

      Domanda 1

      Phone call Interview: Physical Design Flow. What problems did you face ? How to remove Setup violation ? How to remove Hold violation ? Unix commands: ls, cp, grep what is the command to check processes running ? How to run process in background ? softlink command how to check disk usage ? Perl questions: chop vs chomp array, hash, default scalar sign. what is th difference between array and hash when we do indexing ? Logic: he gave me one boolean exp to solve. latch vs flop sram vs dram ? which one is volatile? D FF using MUX D FF operation Comp Arch: pipeline ? cache ? virtual memory ? TLB ? what is the set size for fully associative cache ? Direct associative ? he had given me configuration. Verilog: blocking vs nonblocking initial block ? always ? FSM for 0101. moore vs mealy ?(mealy is prone to glitches. This is what he wanted to hear) verilog code for DFF. Physical: electromigration. setup. hold time, skew ? effect of length, width, thickness on resistance. effect of temp, voltage on Delay. Onsite: First round: she was also Trojan :-) (USC Fight On) tell me about urself. why this transition ? (undergrad in Elec&tele, job in software and MS in EE) Physical Design flow ? what to do to remove setup violation? Hold violation ? sizing, MOS structure, VI curve, effect of voltage on delay, temp on delay ? problem on setup and hold using delay values. power minimization techniques. She was going in depth. Thats it. Second round: Unix commands: how to find .txt files, copy files from one directory to another. find files with particular string. how to execute unix commands in perl script ? (ANS: use exec before each unix command and done) use strict ? what is tht #! usr/bin/perl we write at the start of program ? C vs perl ? Read the file(set up vioations). there are 1000 lines in that file. Print 5 worst delays. array vs linked list with respect to memory allocation. pipeline ? stages ? which CPU is better ? 1GHz vs 2 GHz. Third round: Physical design flow. behavioral: situation when you had conflict with your friend. how you handled situation. how you divide work while working in group. how will you avoid conflict ? (Divide work) how you do finish work before deadline? when you start working on something, you get some problems, you solve it then how do you avoid same mistake in future.(I will note it down. he wanted to hear this) skew, seup time, hold time. Fourth round: Physical Design Flow, synthesis steps, APR steps, problems related to setup and skew.
      Rispondi alla domanda
      28

      Altre recensioni di colloqui per Graphics Hardware Engineer presso Intel Corporation

      Colloquio per Graphics Hardware Engineer

      7 nov 2022
      Dipendente anonimo
      Nuova Delhi
      Offerta accettata
      Esperienza positiva
      Colloquio nella media

      Candidatura

      Ho presentato la mia candidatura tramite segnalazione di un dipendente. La procedura ha richiesto 2 giorni. Ho sostenuto un colloquio presso Intel Corporation (Nuova Delhi)

      Colloquio

      I had been working as an intern at Intel for 9 months. Then I had undergone an interview for a graphics verification/validation team. There were two rounds(both technical), and they asked about my internship experiences, project works, and questions related to digital electronics, verilog code. My interviews were through and after 15 days I got my selection mail from HR.

      Domande di colloquio [2]

      Domanda 1

      FIFO explanation and verilog code for it
      Rispondi alla domanda

      Domanda 2

      Basic understanding of digital electronics
      Rispondi alla domanda

      Colloquio per Graphics Hardware Engineer

      8 gen 2022
      Dipendente anonimo
      San José,
      Offerta accettata
      Esperienza positiva
      Colloquio difficile

      Candidatura

      Ho presentato la mia candidatura online. La procedura ha richiesto più di una settimana. Ho sostenuto un colloquio presso Intel Corporation (San José, ) nel mese di dic 2021

      Colloquio

      2 entrevistas, una de conceptos y otra de técnica-práctica, empleador super ameno, te guían, preguntas de programación OOP, verificación, diseño lógico, verilog, electrónica digital, arquitectura de computadoras, Python, pseudocódigo, UVM/OVM

      Domande di colloquio [3]

      Domanda 1

      Qué es pipeline?
      Rispondi alla domanda

      Domanda 2

      que es SRAM, DRAM, diferencias?
      Rispondi alla domanda

      Domanda 3

      en OOP, Qué es una clase, objeto, herencia, polimorfismo?
      Rispondi alla domanda
      1

      Colloquio per Graphics Hardware Engineer

      27 ott 2021
      Dipendente anonimo
      Offerta accettata
      Esperienza positiva
      Colloquio nella media

      Candidatura

      Ho sostenuto un colloquio presso Intel Corporation

      Colloquio

      Very technical and four to 5 rounds expected. One behavioral. Be prepared for digital design questions and computer architecture. Prepare for hardware languages too. Focus on problem solving and algorithm based approach.

      Domande di colloquio [1]

      Domanda 1

      Focus on SM, logic design, pipelining and coding
      Rispondi alla domanda
      1