questions are from digital electronics and verilog and computer organisation and architecture and static timing analysis OA: aptitude(20 q 30 mins) analog(20 q 30 mins) digital(20 q 30 mins) after that 20 members shortlisted for ananlog and 20 for digital

2 hours in total : First 30 minutes are built of questions about CV and what you look for in the job. 3 questions: state machine, designing adder from some logic gates and coding