Ho presentato la mia candidatura online. La procedura ha richiesto più di 2 mesi. Ho sostenuto un colloquio presso AMD (Boxborough, MA) nel mese di dic 2011
Colloquio
I had 2 phone interviews over 4 weeks. Generally discussed about current research projects. I was invited to meet the team in Boxborough, MA in December. I had around 7 personal interviews including one during lunch. The interviewers were pretty good asked questions on microarchitecture, projects, object oriented concepts, verification and logic design.
I was informed by the recruiter that they'll have a decision by next day. I was told that the team was interested in my candidacy but wanted to conduct one more interview over Skype. I didn't here back from them for about 4 weeks when they told me that they have already identified a other candidate.
Overall it was very poor and unprofessional job by the team manager and the recruiter.
campus interview . 2 rounds, basic questions from STA , cmos, digital basics , verilog questions, verilog code for asynchronus d flipflop, blocking and non blocking statements, structure of 3 input OR gate, explain about static and dynamic power
1. HR Screen
2. Technical Round
The whole process was around 2 weeks.
You first get a call from the HR and then will answer questions.
If you are successful, you will book a time for a technical interview.
Domande di colloquio [1]
Domanda 1
Tell me the difference between combinational and sequential logic
Ho sostenuto un colloquio presso AMD (Markham, ON)
Colloquio
I was not well prepared, It was basic q and a related to my current role and some basic OSI questions, Also interviewer was great he gave me time to understand the question and helped me with the hints
Domande di colloquio [1]
Domanda 1
A chip was given which performs (001)addition,(010) subtraction, (011)multiplication and division(100) on 8 bit value, it can store 20 operands at a time in a stack and 2 bits for error handling,
Arth overflow
Stack over
1.Questions was to find out end cases and possible errors and how can we handle it in verilog test benches?.
2. Also, How to write those test cases. ?
