Two phone interviews. Both had similar questions asked by different people Pipeline, stages, hazards, how u avoid. How u implement these. Register forwarding implementation. Register renaming implementation. why not many stages in pipeline retire time cache LRU algorithm? Cache sets and ways given. calc the cache size Physical to VA translation!! assembly knowledge? give psuedo code to reverse data in 8 byte reg Second phone screen has almost similar questions. Graphics related quesitons: explain various stages of GPU pipe what happens what's vertex/pixel