Interview was good, Interviewers were friendly, overall experience was good, mostly focused on SRAM and System Verilog. In first round they only concentrated on SRAM design project and second round was with a team lead as they work mostly with system verilog, they asked me to implement a problem in system verilog.

I applied through campus career fair and received an email three days later. I have two phone calls later asking about technical questions. I felt it went well but I was rejected.