Ho presentato la mia candidatura online. La procedura ha richiesto 3 settimane. Ho sostenuto un colloquio presso F5 (San Jose, CA) nel mese di set 2016
Colloquio
I applied online and connected with the Manager on LinkedIn. The while process took about 3 weeks. It was originally for the FPGA Engineer - II position. However, they did not find anyone suitable for the position and downgraded the position to FPGA Engineer - I. The HR then contacted me and set me up for a phone interview with the Hiring Manager and one of his Senior Engineers. The phone interview with the Hiring Manager was mostly resume based. The Sr Engineer asked me Verilog based questions which I had to code on Collabedit (live online coding). The next day, The Hiring Manager set me up for an on-site interview a week from then. He also gave me a project to work on, which I had to present in front of a panel.
The on-site interview was about 5 hours long. Including the panel interview, I had 7 rounds. 3 technical, 3 managerial and 1 panel. All of them were very friendly and made sure I was comfortable. It was a good experience. The technical rounds started simple and they started to increase the difficulty of the questions with each answer of mine. They don't want to see if you know everything, they only wanted to know how one approaches the problem at hand.
Overall, it was a good experience and I was expecting a positive result. Sadly, Lady Luck wasn't on my side :(
Domande di colloquio [1]
Domanda 1
Basic logic design questions that started to get more complex with each answer of mine.
Ho presentato la mia candidatura tramite l'università. La procedura ha richiesto 2 settimane. Ho sostenuto un colloquio presso F5 (Spokane, WA) nel mese di mar 2015
Colloquio
Very long affair. Around 5 hours. They gave me a project to work on about 2 weeks before the interview and much of the interview was explaining my design choices to the team I would be joining. Then there were a lot of 2 on 1 interviews with different members of the team.
Domande di colloquio [1]
Domanda 1
How would you send a signal across clock domains from a fast to a slow domain.
