Ho presentato la mia candidatura online. La procedura ha richiesto 4 settimane. Ho sostenuto un colloquio presso Imagination Technologies (Hyderabad) nel mese di ago 2021
Colloquio
Round -1
Digital Logic Design questions of FFs , Latch ,FIFO
Basics of Verilog ,System Verilog .
UVM related quesionts being asked.
Write SVA for few given problems .
OOPS conepts
GLS and STA basics
Domande di colloquio [1]
Domanda 1
1.Randomizations methods and usage of "SOFT" use-cases.
2.Clock gating and different techniques and use-case
3.Clocking blocks and what's need of skews .w.r.t TB
4.Concept of Metastability in Flip-flops and explanation on topic.
5.Code example : Write Assertion for AXI address channel handshaking.
: Example based on waveform scenario given , develop interface ,driver and sequence UVCs
6.serialize an 8-byte array (bit [7:0] x [8]) to bit [63:0] y using index part-select syntax.
7.why do we sample on clk event in coverage model cg ( events )
Ho sostenuto un colloquio presso Imagination Technologies
Colloquio
The first interview was on the phone for half an hour with simple questions. Then on site interviews for 3 hours with three different teams: hardware design and verification and the manager.
Ho presentato la mia candidatura tramite segnalazione di un dipendente. La procedura ha richiesto 3 settimane. Ho sostenuto un colloquio presso Imagination Technologies (Hyderabad) nel mese di apr 2022
Colloquio
Two rounds of technical interviews.
Well detailed and through interview process.
Questions from verilog, sytem verilog and uvm.
Questions on assertions functional coverage and code coverage
Questions based on computer architecture.
Third round is HR interview process.
