Ho presentato la mia candidatura tramite segnalazione di un dipendente. La procedura ha richiesto più di una settimana. Ho sostenuto un colloquio presso Intel Corporation nel mese di nov 2015
Colloquio
Referral by a friend and I got the email from a engineer directly to ask for the time slot, and got the phone interview a couple of days later, then emailed me the bad news
Domande di colloquio [1]
Domanda 1
The first one is a FSM for a vendor machine and the second one is about CPU pipeline, third one is the how cap and res will be for a long wire then we talked about the job and the company, the gay was nice and tried to help me with the problem I had difficulty, but I still miss one possible situation for the FSM and missed one step for the CPU pipeline. After about half a month I was told no further round, so sad.
Ho sostenuto un colloquio presso Intel Corporation (Guadalajara, Jalisco)
Colloquio
Largo, cansado, solo si tienes conexiones en Intel te llaman, el proceso es largo, las preguntas técnicas son fáciles, sin embargo si eres de otro estado tus posibilidades de ser contratado bajan
Ho sostenuto un colloquio presso Intel Corporation
Colloquio
The interview started with a short introduction about myself. The interviewer then explained the role and the responsibilities. They asked me to describe my final project in detail and followed with a few technical questions.
Domande di colloquio [1]
Domanda 1
Can you walk me through your final project and explain the main technical challenges you handled?
In very much details. Block diagram and code.
Ho sostenuto un colloquio presso Intel Corporation (Heredia)
Colloquio
Apply through the web site, answer some questions about experience and knowledge of Verita in tools.
After that you get an email asking for some more information (availability and such). Next it’s a short phone call to verify your English level.
After that there’s a technical interview and then a final interview
Domande di colloquio [1]
Domanda 1
Had to create a flip-flop with asynchronous and other with synchronous reset using system verilog