Ho presentato la mia candidatura tramite un selezionatore. La procedura ha richiesto 2 settimane. Ho sostenuto un colloquio presso Intel Corporation (Cupertino, CA) nel mese di apr 2016
Colloquio
The interview was considered easier than other companies, basically walked through the resume and asked questions for the work I was done in the previous companies. People were very polite.
Domande di colloquio [1]
Domanda 1
SystemVerilog assertion and functional coverage coding.
Ho presentato la mia candidatura online. Ho sostenuto un colloquio presso Intel Corporation
Colloquio
1 Screening Round and 4 Technical rounds and 1 HR Round conducted. In 1 week interview scheduled and offer released in 2 to 3 weeks.
Questions from system verilog and uvm, Project related question which have hands on experience
Ho presentato la mia candidatura online. Ho sostenuto un colloquio presso Intel Corporation nel mese di gen 2023
Colloquio
UVM question System Verilog Question AMBA Buses, AXI, AHB and APB When and how would you perform a factory override? Describe the differences between components and objects in UVM. How do you connect a DUT interface to a UVM component? Which UVM phase do you integrate to for phase runs for test cases? How would you reduce the time it takes to initiate a UVM run phase?
Domande di colloquio [1]
Domanda 1
describe UVM Phases and difference bet run phase and main phase
Ho presentato la mia candidatura online. La procedura ha richiesto 2 mesi. Ho sostenuto un colloquio presso Intel Corporation (Santa Clara, CA) nel mese di gen 2023
Colloquio
Ask me Verilog, SystemVerilog, UVM basics, C/C++ problem-solving questions, and about my resume projects. Focus on digital design, verification concepts, coding logic, and real-time debugging approaches.more on resume focused and old projects in detailed manner.
