I had a phone interview and was later called for an onsite interview. There were multiple positions available in various aspects of ASIC design, from RTL design, DFT, Physical Design etc. They were testing my basics in each round. Basic questions on setup, hold time and special scenarios were given on the board and i was asked to solve them. What happens if nmos and pmos are inverted in an inverter. Basics on scan chains and Boundary Scan design (as it was on my course). Questions on synthesis, basic constraints in DC, like set_input_delay, set_output_delay, set_max_fanout, set_clock_latency. FSM design and clock frequency divider ckts, by2 and by3. Later they asked 50% duty cycle in freq divided by 3 ckt. Asked me to code an up-down counter in verilog on white board. Asked about parameters and their usage in verilog. Asked some questions on synchronizing data signals between different clock domains. Physical design round went a little unexpected. I was asked about what the properties of different metal layers might be. Which has higher cap and which has higher resistance. Other basic questions like clock skew and what is done to reduce clock skew. And some questions on various low power designs: power gating, clk gating, using low Vdd etc.

Sent resumé and cover letter via school co-op program. Got an email from co-op to meet at the office down by Marine-Gateway. There will be two interviewers and a bunch of questions about cover letter and resumé