Ho presentato la mia candidatura di persona. La procedura ha richiesto 3 mesi. Ho sostenuto un colloquio presso Micron Technology (Bengaluru) nel mese di ago 2015
Colloquio
First round was a telephonic interview. Lasted around one hour. Questions were mostly on the basics of semiconductor devices like pn junction and band diagrams. My PhD thesis involved Schottky diodes so there were some questions on Schottky barrier heights. Some questions on various kinds of photodetectors (MSM and pin) and their relative merits and demerits. Again, this was asked as I worked on it for my PhD.
Second round was an on-site interview that lasted the entire day from morning to evening. Started with me making a presentation of about 15 minutes on my thesis work. This was followed by individual interviews with each person in the team. Each interview lasted about 45 minutes and there were 6 people in the team. So the entire process took from morning to evening. Questions were mostly focussed on the basics of semiconductor devices like MOSFETs, BJTs, MOS CV curves and the effect of non-idealities. MOS CV curve questions were asked by every one of the interviewers. One question on device modelling (model a sigmoid curve) and one question on aptitude (100 windows, all open. First toggle all multiples of 2, then toggle all multiples of 3, and so on. Which windows are open at the end of all the toggling?)
Domande di colloquio [1]
Domanda 1
Draw the MOS CV curve for a p-bulk Si MOS device. Describe the effect of non-idealities like interface charges and traps.
Ho sostenuto un colloquio presso Micron Technology (Singapore)
Colloquio
The interview was pretty easy. They were asking about mosfet fundamentals and short channel effects like DIBL,GIDL etc. they asked c-v plots of mosfet and moscap. They also asked few questions on analog electronics
Ho sostenuto un colloquio presso Micron Technology
Colloquio
One campus inverter; four technical questions are asked regarding VLSI logic circuit design Why does a NAND memory cell have a finite number of write/erate cycles? Create a XOR gate with only 4 NAND gates
Domande di colloquio [1]
Domanda 1
Why does a NAND memory cell have a finite number of write/erate cycles? Create a XOR gate with only 4 NAND gates
Ho presentato la mia candidatura tramite l'università. La procedura ha richiesto un giorno. Ho sostenuto un colloquio presso Micron Technology (New York, NY)
Colloquio
2 rounds of interview, both technical and online
Started with basic pn junction and covered till mosfets. 3 people were there in the panel, they were warm and didn't make u nervous
Domande di colloquio [1]
Domanda 1
Explain pn junction in reverse and forward bias, explain the energy spectrum, the band energy, the fabrication of mosfet, effect on the junction of the diode with variation in biasing, working of bjt, mosfet in intricate details