Domanda di colloquio di NVIDIA

Phone interviews : CMOS basics, usual some gate/logic using one gate, timing related questions, FIFO depth, max in array, palindrome Onsite : CDC - a lot on various techniques and improvements from one to another, clock MUX logic, Clock dividers, FSM , Timing related question based on designs above

Risposta di colloquio

Anonimo

17 giu 2020

I would also check teamblind.com