Resume was shortlisted and I was called for the interview. 2 rounds of Technical Interview for Design & Verification. Verification Interview was on state machine design, Verilog coding & scheduling problems. Should be easy if you are strong in Digital Eletronics. Design Interview was standard. The interviewer asked me to design an Asynchronous FIFO; False paths, Multi-Cycle paths; Clock Domain Conversion; 1 bit transfer between 2 different clocks; Metastability etc..

I had 6 rounds total. The first two were with senior directors who really drilled into my past projects and took time to walk me through the team's work and org structure — they seemed genuinely engaged. Then I had three rounds with staff engineers. We covered some coding questions I wrote edge detection logic and an FSM, but I made a couple of mistakes on the first pass that I caught and corrected when the interviewers pointed them out. We also talked about DV concepts like reference models and how to build self-checking testbenches. The final round was with a senior MTS from the Markham office, and it was pure behavioral no technical questions, just asking about my background and team fit.