Asking about one thing in SV if can't pass it the whole interview will be logic design. Study well the book of SV for verification and solve all its exercises .
The main qustions distributed over Digital Design, GP , Digital verification
verilog code sys verilog STA and UVM constrains SVA Arrays different data types and different syntax also FF and Metastability
Ho presentato la mia candidatura online. Ho sostenuto un colloquio presso Si-Vision (Il Cairo, ) nel mese di gen 2020
Colloquio
technical exam in paper for 2 hours it was about logic design and logic circuit reduction and object oriented programing and verilog and system verilog
the next phase was technical interview with 2 engineers
after this interview they emailed me with small task to solve and gave me 2 weeks to solve it and return to the company and do presentation about my solution
Domande di colloquio [1]
Domanda 1
it was general discussion about logic design and he gave me discribtion about circuit and asked me to leocate the signals that i should select for testing and verifying
they gave me small task about an alu and i am supposed to write verification code in system verilog for it , actually they were very generous they provide the matrials to learn more about system verilog and how to write such a design
