45 minutes long. Asked about projects on resume, then had to debug some wrong Verilog code, and fix it. Asked about experience in Verilog, SystemVerilog, and debugging. Especially verification, ask how you used verification in previous work.
Domande di colloquio [1]
Domanda 1
Asked me to debug a Adder Module in Verilog that was incorrect.
Ho presentato la mia candidatura tramite l'università. Ho sostenuto un colloquio presso Silicon Labs (Hyderabad) nel mese di nov 2022
Colloquio
Resume-based shortlisting had been done. There were three interview rounds. Two technical and one HR round. The first round was based on digital electronics basics and Verilog programming. The second round was based on the projects and in-depth knowledge of digital circuits, and computer architecture. Hr round had expected questions.
Domande di colloquio [1]
Domanda 1
1) Write the full adder code and testbench in Verilog? 2) Truth table of JK and D flip flop? 3) Why do glitches occur, and how to solve them? 4) Implement NAND gate using mux?
