Being a fresher digital electronics is the key. More question would arise on digital and few on logical questions if you have knowledge on system verilog, verilog and UVM, it will even beneficial

Interview went smooth. Mainly focused on sv and verilog.. it was 2 round interview in which one is written test and the other is online interview. In written test, they ask aptitude, expected output and sv concepts. In online round, they ask oops, inheritance, polymorphism etcc