Ho presentato la mia candidatura online. Ho sostenuto un colloquio presso TSMC nel mese di apr 2024
Colloquio
For a physical design (VLSI entry-level) interview and written test, you should prepare on the following topics:
Basics of VLSI design
CMOS technology and fabrication process
Circuit design and analysis
Logic design and digital electronics
RTL (Register Transfer Level) design
Physical layout design
Timing analysis and closure
Power analysis and optimization
Floorplanning and placement
Routing and congestion analys
Domande di colloquio [1]
Domanda 1
What are "Spare Cells" and why it is used?
Why do you make clock as Ideal during floorplan & Placement Stage?
What are the different Checks we do in the CTS stage?
What if Setup is failed after manufacturing of chip?
How will you fix Hold?
What is the Importance of useful Skew?
What are DRV Checks and why do we check that?
What is the cross talk? How it will effect the performance?
Cross delay or Cross talk noise is note generally. Why?
A Blocks having 7 Metal layers and same block having 10 metal layer, which will function better and why?
How will you define the shape of the Die?
Ask about my peospnal infomation resume and experience and ask about tech question. Also ask about when you can start working. Lastly, he ask what question do you have for this position
