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      Ricerche correlate: Recensioni su VVDN Technologies | Offerte di lavoro di VVDN Technologies | Stipendi di VVDN Technologies | Benefit di VVDN Technologies
      Colloqui di VVDN Technologies Colloqui per FPGA Engineer presso VVDN Technologies Colloquio di VVDN Technologies


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      Colloquio per FPGA Engineer

      24 ago 2021
      Candidato anonimo a colloquio
      Nuova Delhi

      Altre recensioni di colloqui per FPGA Engineer presso VVDN Technologies

      Colloquio per FPGA Engineer

      27 mag 2021
      Dipendente anonimo
      Offerta accettata
      Esperienza positiva
      Colloquio nella media
      Offerta rifiutata
      Esperienza positiva
      Colloquio nella media

      Candidatura

      Ho presentato la mia candidatura tramite segnalazione di un dipendente. Ho sostenuto un colloquio presso VVDN Technologies (Nuova Delhi) nel mese di ago 2021

      Colloquio

      Two online test followed by 2 technical interviews. Process ended with a HR round. Questions were moderate to difficult from digital and verilog. Second Technical round was a bit tough than the first.

      Domande di colloquio [1]

      Domanda 1

      Questions from digital and verilog
      Rispondi alla domanda
      1

      Candidatura

      Ho presentato la mia candidatura tramite un'altra fonte. Ho sostenuto un colloquio presso VVDN Technologies

      Colloquio

      Medium difficulty. A test (consists of Digital, English, Aptitude and Logical Reasoning Questions) followed by two technical rounds, followed by HR round. Technical rounds will be focused on real world application and the projects that they are working on. Understanding of protocols as a fresher is a big plus.

      Domande di colloquio [1]

      Domanda 1

      General Digital Electronics and protocol based questions like AXI, UART, etc
      1 risposta
      1

      Colloquio per FPGA Engineer

      21 ott 2016
      Candidato anonimo a colloquio
      Eranakulam, Kakkanad
      Nessuna offerta
      Esperienza neutra

      Candidatura

      Ho presentato la mia candidatura online. La procedura ha richiesto un giorno. Ho sostenuto un colloquio presso VVDN Technologies (Eranakulam, Kakkanad) nel mese di ott 2016

      Colloquio

      As a fresher in Embedded technology, with a high expectation and enthusiasm I to Kerala only to attend this interview. I was invited as a response to my mail. The interview was finished today (12/10/2016) at 10.00 am. It had 30 purely technical qsns from digital electronics. I couldn't clear the exam. Most of the candidates were with recommendations. But even they too couldn't get through. It have overheard from the candidates that, the interview was just a formality and the posts were fixed for some candidates who are the batch-mates/ colleagues of other employees. Three of them were selected.

      Domande di colloquio [5]

      Domanda 1

      1. How many bits are required to store BCD digit?
      1 risposta

      Domanda 2

      2. How many bits are required to store ASCII digit?
      1 risposta

      Domanda 3

      3.How to do multiplication in VHDL without multiply?
      Rispondi alla domanda

      Domanda 4

      4. D mux implementication using J K?
      Rispondi alla domanda

      Domanda 5

      5. What is the frequency of the MSB of 3 bit counter of frequency f hz 6.binary to hexa decimal conversion 01011010 7.. 625 in decimal to binary 8.two switches are at staircase connection for a bulb one switch in the first floor other in second floor...the operation of the bulb is based on which gate 9. A 3 bit counter with last gate connected to not and what is the range of counting Ans is 0000to 0101 10. Clipper circuit with zener parallel to apply and to obtain the output voltage waveform 12. A resistor circuit with all resistances are 1ohm...and current is 1amp. To find the voltage across a and b 13. Zener based circuit and to obtain output waveform with input sine wave given 14.which diode is on 15. Demux with logic 0utput... The logic 0outputs given to or gate and all inputs are inverted and obtain output function 16.a mux with 4inputs and 3inputs are high and one is inverted and output of mux given to logic low chip select.... The address range that can be accessed by the peripherals are 17.counter with each flip flop has Some ns delay and some ns setup delay.. What is the frequency of operation 18. Shift registers output after 2clocks serial in parallel out 19. What is the max and min values of 2s complement n bit number 20. Steady state response question 21. Frequency division one more question in counters
      Rispondi alla domanda
      17