Ho sostenuto un colloquio presso Google (Tel Aviv)
Colloquio
The first two interviews focused on writing a driver for a specific protocol provided during the session, followed by several iterations of refining the protocol and adapting the driver accordingly. The third interview covered a basic programming question, some fundamental questions about coverage — its purpose, the difference between code coverage and functional coverage — and designing a simple configurable shifter module in Verilog. The final interview was behavioral, centering on how I handled various situations in the workplace.
Altre recensioni di colloqui per Design Verification Engineer presso Google
Ho presentato la mia candidatura online. La procedura ha richiesto un giorno. Ho sostenuto un colloquio presso Google (Bengaluru) nel mese di lug 2025
Colloquio
Round 0 – Resume Screening: I optimized my resume using ATS tools like ResumeWorded, aligning keywords with the job description and quantifying impact (e.g., “Improved functional coverage by 30% using constraint randomization”).
Round 1 – SystemVerilog Fundamentals: Covered arrays, IPC, fork-join, OOP (inheritance, polymorphism), constraints (weighted, implication), and assertions. Emphasis was on explaining concepts clearly and debugging edge cases.
Round 2 – UVM Concepts: Focused on class hierarchy, factory methods, config_db vs resource_db, and RAL integration. I demonstrated how I build modular, reusable testbenches using UVM phases and configuration techniques.
Round 3 – Problem Solving & Debugging: Included designing and verifying FIFO and protocol-based modules. I debugged failing simulations using waveform analysis and refined coverage goals using targeted sequences.
Domande di colloquio [1]
Domanda 1
How would you debug a failing simulation where coverage is not met?
was a long and interesting process, it contains four interviews, it was a difficult process but a beneficial one, for each interview I learned a lot.
in the last interview
