Ho sostenuto un colloquio presso Microchip Technology (New York, NY)
Colloquio
I had a tough interview, mainly foccused on standard systemverilog/ verilog questions along with some programming questions in designing. Some detailed question of explaning on static timing analysis and clock domain crossing.
Domande di colloquio [1]
Domanda 1
Setup time and hold time calculations of a design? Optimization of FPGA design interms of power, timing while makking frequency efficient.
