2 rounds of interviews. First round was screening mainly, simple questions on digital design, computer architecture principles (branch prediction, cache coherency, pipelining, etc.) Second round involved coding questions in Verilog and C++. It also involved drawing the state machine of a hypothetical scenario and then coding the Verilog RTL of the correct solution.

I have done only a screening round, and I have prepared all the DV topics, but they asked me coding questions instead. The questions are easy to moderate, like implement a function for randc in Python or System Verilog without using any built-in functions