Ho presentato la mia candidatura online. La procedura ha richiesto 4 settimane. Ho sostenuto un colloquio presso Synopsys nel mese di giu 2018
Colloquio
Got a call from the recruiter for scheduling a phone interview. Phone interview was just for 30 mins. Was asked basic digital design questions. After a week got I got an email to check availability for onsite interview. I provided the dates and the interview was set up
Domande di colloquio [4]
Domanda 1
Design basic logic gates (AND, XOR) using a 2to1 mux. Write a module which will take clk as an input and output a clk divided by 3. Important to note that generated clock needs to be an output of the Flop.
Was asked about basic protocols for PCIE. Basic questions on CDC. Types of violations that the CDC tools complain - eg: no_sync, combi logic before double sync, multi bit double syncing, re-convergence etc.
Code async reset FF and sync reset FF. What are the dis/advantages of one over the other.
How to synchronize a data bus, which has no control. Interviewer was basically trying to poke at the approach to solve that problem.
Write clock domain has a burst rate of 80 writes per 100 clocks. Read clock domain reads at a rate of 8 data words in 10 clocks. Data Buffer sizing to not cause overflow
Asked to design a 2 request arbiter.
A module has 3 input and 5 output ports. Had a discussion for rest of the interview on that design. Basically the interviewer was trying to understand what I need to come up with a design. Like, do you a clock, what are you control signals, what is the functionality etc
Ho presentato la mia candidatura online. La procedura ha richiesto 5 settimane. Ho sostenuto un colloquio presso Synopsys (Mississauga, ON) nel mese di giu 2025
Colloquio
One interview with the team manager to go over my previous academic and work experience. I was told what would be expected of the position and I was asked a couple of technical questions at the end. Successful applicants would be invited for an onsite interview.
Domande di colloquio [1]
Domanda 1
I was asked to write the RTL code for an asynchronous receiver in Verilog
Ho sostenuto un colloquio presso Synopsys (Bengaluru)
Colloquio
Round one : asked about Fifo ,it's functionality and verilog code. Two puzzles like the very famous 1000 bottle and the 8 queen puzzle, then some basic digital electronics questions
Ho sostenuto un colloquio presso Synopsys (Maia, Oporto)
Colloquio
2 Interviews
1st technical interview - Some basic concepts about digital design. Went good. Basic position so in general the manager wanted to know which projects have I worked on in the past.
2nd HR interview - Personal interview with common questions.
Domande di colloquio [1]
Domanda 1
Question related to FSMs, which diagram describes the implementation better.
