Ho presentato la mia candidatura di persona. La procedura ha richiesto 4 settimane. Ho sostenuto un colloquio presso Synopsys (Bengaluru) nel mese di dic 2018
Colloquio
I was asked questions on Verilog/VHDL basics, Testbench concepts, RTL coding, FSM models. system verilog assertions etc. questions related to past work and VLSI flow. Digital design concepts like adders, fsm, logic optimizations.
Domande di colloquio [1]
Domanda 1
I was asked questions on Verilog/VHDL basics, Testbench concepts, RTL coding, FSM models. system verilog assertions etc. questions related to past work and VLSI flow. Digital design concepts like adders, fsm, logic optimizations.
Ho sostenuto un colloquio presso Synopsys (Canonsburg, PA)
Colloquio
There were several stages to the interview process. Required a lot of time, but in the end, it was well worth the effort. The interview panel was very supportive and encouraging.
The interview process was seamless, featuring a moderate level of questions. The supportive demeanor of the interviewer enhanced the overall experience, making it smooth and conducive to a positive interaction.
Domande di colloquio [1]
Domanda 1
It covered concepts of Digital Circuits, VLSI Design. Combinational vs Sequential circuits, FFs, FSM.
Ho presentato la mia candidatura tramite l'università. Ho sostenuto un colloquio presso Synopsys (Bengaluru) nel mese di set 2022
Colloquio
The Interview was of 3 rounds.
1. Basic Introduction and 1 technical question by the Manager.
2. Technical round by a technical lead.
3. Technical round by another technical lead.
Domande di colloquio [1]
Domanda 1
If there are setup and hold violations and you are at the last stage what would you choose to fix either setup? or hold? and why?
