Ho presentato la mia candidatura online. La procedura ha richiesto 4 settimane. Ho sostenuto un colloquio presso Meta (Oslo) nel mese di gen 2024
Colloquio
First hr call on phone then 1st round with hiring manager. next is technical and behavioural round where in technical round they ask me about sv and uvm, gave a problem to code based on sv.
One basic round the 5-6 loop interviews.if we qualify 1 round loops interviews will be there.all questions are basis.mostly about sv constraints. Last round will be focused on test plan creation.
Ho presentato la mia candidatura tramite segnalazione di un dipendente. La procedura ha richiesto 2 settimane. Ho sostenuto un colloquio presso Meta (Bengaluru) nel mese di lug 2025
Colloquio
1 screening round of 45 minutes if thorugh then ,3 technical rounds of 45 mins each and atlast 1 HR round of 45 mins. Screening for basic knowledge and coding. Three technical where in depth knowledge and coding will be tested.
Domande di colloquio [1]
Domanda 1
Constraint randomization based question linking to AXI and memory filling
Ho presentato la mia candidatura online. La procedura ha richiesto 5 giorni. Ho sostenuto un colloquio presso Meta (Bengaluru) nel mese di feb 2025
Colloquio
45 mins technical online interview. Interviewer was in PST timezone. Interview on coderpad. The interviewer asked about my professional journey so far and got started with coding interview. An initial document was shared with me prior to setting up the interview that listed the topics they can possibly ask in the interview for preparation. They asked me to fill up 4-5 timeslots where I can take an interview and in about 1-2 days the interview slot was finalized.
Domande di colloquio [3]
Domanda 1
Write an SV constraint to generate 4 non-overlapping memory regions of size 32,64,128,256 in 4k memory region.
Write a uvm driver for a simple valid-ready protocol.
- When data is available assert the valid
- Keep the data stable and valid high until ready is asserted
- De-assert the valid once ready is asserted
interface if
input clk;
logic [15:0] Data;
logic Valid;
logic Ready;
endinterface
